1. Field of the Invention
The invention relates generally to a NAND type flash memory device, and more particularly to, a word line decoder having a switch structure for applying a negative voltage to a word line, and transistors.
2. Description of the Prior Art
A NAND type flash memory device, one of non-volatile semiconductor memory devices, has a level of integration and a memory capacity corresponding to DRAM. Due to these advantages, the NAND type flash memory device has been increasingly used. The NAND type flash memory device has basically a structure in which a memory string where a plurality of memory cells are serially connected is serially connected between a bit line and a source line. A plurality of the memory cells are arranged to form a memory cell array. The memory cells connected to one word line with the memory string intervened them form a page unit or a byte unit. In order to perform a read operation or a write operation by selecting a given cell of the flash memory device, a corresponding cell is selected by word line and bit line select signals. The decoder for selecting the word line is called a word line decoder.
A conventional word line decoder and memory cell will be below described by reference to FIG. 1 and FIG. 2.
FIG. 1 is a structure of the conventional word line decoder and memory cell. The structure includes a row decoder and charge pump 10, a block-driving unit 12 and a memory cell array 14.
Referring now to FIG. 1, a region of a memory cell array 14 is divided into a plurality of cell blocks. One cell block includes a plurality of strings. At this time, each of the strings is intervened between one bit line B/L and a common source line. One cell block includes a string select line SSL, a plurality of word lines W/L and a ground select line GSL. Also, the block-driving unit 12 includes a string control line SS, a plurality of word control lines S, a ground control line GS and a plurality of transistors for driving the blocks. The plurality of the transistors are controlled by the row decoder and charge pump 10 to control only one cell block. The transistor includes one string driving transistor connected to the string control line SS, a plurality of word driving transistors connected to the word control lines S, and one ground driving transistor connected to the ground control line GS.
A method of driving the NAND type flash memory device shown in FIG. 1 will be below explained.
For example, if a desired cell transistor at the cell array 14 region is to be selectively programmed, 0V is applied to a semiconductor substrate in which the cell array 14 region is formed, that is, the bulk region and the common source line of the cell transistor. Also, 0V is applied to the bit line and the ground control line connected to the selected cell transistor. At this time, a program inhibition voltage is applied to all of not-selected bit lines. Also, a program voltage is applied to the word control line connected to the selected cell transistor. A voltage that is sufficiently higher than the program voltage applied to the word control line, is applied to the transistor of the block driving unit 12, so that the block driving transistors can be sufficiently turned on. That is, the string driving transistors, the word driving transistors and the ground driving transistor are all turned on. At this time, a program operation for the selected cell transistor is performed by means of a F-N tunneling current. Program inhibition of the not-selected cell transistors is performed by means of a self-boosting phenomenon.
FIG. 1 will be further explained by reference to FIG. 2.
FIG. 2 is a detailed circuit diagram of the word line decoder shown in FIG. 1. The word line decoder includes a row decoder 20, a high-voltage control circuit 22 and a driving transistor 24.
The row decoder 20 includes a first NAND gate NAND1 and a first NOR gate NOR1. An output of the first NAND gate is inputted to the first NOR gate NOR1 and an output of the first NOR gate NOR1 is inputted to the high-voltage control circuit 22. An address signal (ADx) for selecting the block is applied to the first NAND gate NAND1 of the row decoder 20. A signal (Select_LeftRight) for selecting a given plain along with the output signal of the first NAND gate is inputted to the first NOR gate NOR1. Therefore, if a given cell is selected, the output of the row decoder 20 becomes HIGH. If the cell is not selected, the output of the row decoder 20 becomes LOW.
The high-voltage control circuit 22 includes a second NAND gate NAND2, transistors M1, M2, M3, M5, an inverter INV1 and capacitors C1, C2. An output signal of the row decoder 20 and the clock signal (CLK) are inputted to an input of the second NAND gate NAND2. A power supply voltage (Vcc) is applied to the gate of the transistor M1, and a voltage Vpp that is same to or lower than the power supply voltage is applied to one inputs of the transistors M3 and M5.
The driving transistors 24 includes a string driving transistor connected to the string control line SS, a plurality of cell transistors connected to the word control lines S, and a ground driving transistor connected to the ground control line GS. The driving transistors may be implemented using NMOS.
In the above, if the output of the row decoder 20 is HIGH, the high-voltage control circuit 22 outputs (Vpp+Vtn) using the clock signal (CLK). At this time, Vtn is the threshold voltage of the driving transistors 24. Therefore, the driving transistors 24 are turned on. If the positive voltage is applied to the string control line SS, the word control lines S and the ground control line GS, Vtn is applied to the string select line SSL, the word lines WL and the ground select line GSL. The capacitors C1, C2 serve to boost the applied Vpp in order to make it (Vpp+Vtn). If the output of the row decoder is LOW, the output of the second NAND gate NAND2 is regardless of the clock signal (CLK) and the capacitors C1, C2 do not serve to boost Vpp. Therefore, as LOW inputted from the row decoder 20 is intact outputted through transistor M1, the driving transistors 24 is turned off. Also, the positive voltage applied to the string control line SS, the word control lines S and the ground control line GS is not transferred to the string select line SSL, the word lines WL and the ground select line GSL.
The conventional word line decoder can apply only the positive voltage to the memory cell array. This is because only the positive voltage can be applied to the string control line SS, the word control lines S and the ground control line GS of the driving transistors 24 but the negative voltage could not be applied to them.
A reason that the negative voltage could not be applied to the driving transistors 24 will be below described by reference to FIG. 3. FIG. 3 is a cross sectional view of the flash memory cell in which the negative voltage is applied to the driving transistors shown in FIG. 2. If the driving transistor is to be implemented using NMOS, a P well is grounded. If xe2x88x9210V of the negative voltage is applied to the source S, the NMOS transistor does not properly operate due to a forward condition of the PN junction.
Therefore, in the conventional NAND type flash memory device, the program, erase and read operations could have been performed for the memory cell selected using the positive voltage only. In particular, as higher voltage is used during the erase operation than during the program operation, a stress is applied to not-selected blocks due to a well bias. There is a problem that data of the memory cell is distorted.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a word line decoder in a NAND type flash memory device in which a negative voltage can be applied to word lines of the flash memory cell.
In order to accomplish the above object, the word line decoder in the NAND type flash memory device, for decoding a word line select signal by which a given memory cell is selected comprises a row decoder for receiving an address of the given memory cell to produce a signal informing that the given memory cell is selected or not selected, a control unit for outputting a positive voltage if the signal informing that the given memory cell was selected from the row decoder is received and for outputting a negative voltage if the signal informing the given memory cell was not selected is received, and a driving unit having NMOS transistors for outputting the negative voltage inputted to sources of the NMOS transistors to drains of the NMOS transistors if the positive voltage outputted from the control unit is applied to gates of the NMOS transistors, and for prohibiting the negative voltage inputted to the sources from being outputted to the drains if the negative voltage outputted from the control unit is applied to the gates of the NMOS transistors, wherein the negative voltage inputted to the sources of the NMOS transistors is applied to a P well of the NMOS transistors.
In order to accomplish the object, the control unit comprises an inverter connected between a first input terminal and a first node, for inverting an input signal, a first NMOS transistor connected between the first node and a second node, wherein a gate of the first NMOS transistor is connected to the power supply voltage, a first PMOS transistor connected between the first node and a third node, wherein a gate of the first PMOS transistor is connected to the ground, a second PMOS transistor connected between the second node and a second input terminal, wherein a gate of the second PMOS transistor is connected to an output terminal, a second NMOS transistor connected between the third node and a third input terminal, wherein a gate of the second NMOS transistor is connected to the output terminal, a third PMOS transistor connected between the second input terminal and the output terminal, wherein a gate of the third PMOS transistor is connected to the second node, and a third NMOS transistor connected between the third input terminal and the output terminal, wherein a gate of the third NMOS transistor is connected to the third node.